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Dual Bootstrapped, 12 V MOSFET Driver with Output Disable ADP3418
FEATURES
All-in-one synchronous buck driver Bootstrapped high-side drive 1 PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float the output per Intel(R) VR 10 and AMD OpteronTM specifications
GENERAL DESCRIPTION
The ADP3418 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated, synchronous, buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 30 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3418 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the highside and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdowns. The ADP3418 is specified over the commercial temperature range of 0C to 85C and is available in an 8-lead SOIC package.
APPLICATIONS
Multiphase desktop CPU supplies Single-supply synchronous buck converters
FUNCTIONAL BLOCK DIAGRAM
12V
CVCC VCC
4
D1 CBST2 CBST1 Q1 RG RBST1
7
ADP3418
1
BST DRVH
IN 2
8
DELAY SW
TO INDUCTOR
CMP
S R
Q
Q DELAY
VCC 6
5
DRVL PGND
Q2
CMP 1V
6
3
OD
Figure 1.
(c)2010 SCILLC. All rights reserved. May 2010 - Rev. 6
Publication Order Number: ADP3418/D
03229-B-001
ADP3418 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Timing Characteristics..................................................................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Low-Side Driver............................................................................ 9 High-Side Driver ...........................................................................9 Overlap Protection Circuit...........................................................9 Application Information ................................................................ 10 Supply Capacitor Selection ....................................................... 10 Bootstrap Circuit ........................................................................ 10 MOSFET Selection ..................................................................... 10 High-Side (Control) MOSFETs ................................................ 10 Low-Side (Synchronous) MOSFETs .........................................11 PC Board Layout Considerations..............................................11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
Rev. 6 | Page 2 of 13 | www.onsemi.com
ADP3418 SPECIFICATIONS1
VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 85C, unless otherwise noted. Table 1.
Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay2 LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay2 Timeout Delay Symbol VCC ISYS Conditions Min 4.15 BST = 12 V, IN = 0 V 2.6 -1 tpdhOD tpdlOD See Figure 3 See Figure 3 3.0 -1 VBST - VSW = 12 V VBST - VSW = 12 V See Figure 4, VBST - VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST - VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST - VSW = 12 V VBST - VSW = 12 V 1.8 1.0 35 20 40 20 1.8 1.0 25 21 30 10 240 120 0.8 +1 3.0 2.5 45 30 65 35 3.0 2.5 35 30 60 20 25 20 0.8 +1 40 40 3 Typ Max 13.2 6 Unit V mA V V A ns ns V V A ns ns ns ns ns ns ns ns ns ns
trDRVH tfDRVH tpdhDRVH tpdlDRVH
10
trDRVL tfDRVL tpdhDRVL tpdlDRVL
See Figure 4, CLOAD = 3 nF See Figure 4, CLOAD = 3 nF See Figure 4 See Figure 4 SW = 5 V SW = PGND
5
90
1 2
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
Rev. 6 | Page 3 of 13 | www.onsemi.com
ADP3418 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC BST DC <200 ns BST to SW SW DC <200 ns DRVH (DC) DRVH (<200 ns) DRVL (DC) DRVL (<200 ns) IN, OD Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Junction-to-Air Thermal Resistance (JA) 2-Layer Board 4-Layer Board Lead Temperature (Soldering, 10 sec) Infrared (15 sec) Rating -0.3 V to +15 V -0.3 V to VCC + 15 V -0.3 V to +36 V -0.3 V to +15 V -5 V to +15 V -10 V to +25 V SW - 0.3 V to BST + 0.3 V SW - 2 V to BST + 0.3 V -0.3 V to VCC + 0.3 V -2 V to VCC + 0.3 V -0.3 V to +6.5 V 0C to 85C 0C to 150C -65C to +150C 123C/W 90C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 6 | Page 4 of 13 | www.onsemi.com
ADP3418 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST 1 IN 2
8
DRVH
03229-B-002
SW TOP VIEW OD 3 (Not to Scale) 6 PGND VCC 4 5 DRVL
7
AD3418
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic BST IN OD VCC DRVL PGND SW DRVH Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 F. Logic Level Input. This pin has primary control of the drive outputs. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with a ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck switching node, close to the upper MOSFET's source. It is the floating return for the upper MOSFET drive signal. Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 6 | Page 5 of 13 | www.onsemi.com
ADP3418 TIMING CHARACTERISTICS
OD
tpdlOD
tpdhOD
DRVH OR DRVL
10%
Figure 3. Output Disable Timing Diagram
IN
tpdlDRVL tfDRVL
DRVL
tpdlDRVH
trDRVL
tfDRVH tpdhDRVH trDRVH
DRVH-SW
VTH
VTH
SW
1V
Figure 4. Timing Diagram--Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted
Rev. 6 | Page 6 of 13 | www.onsemi.com
03229-B-004
tpdhDRVL
03229-B-003
90%
ADP3418 TYPICAL PERFORMANCE CHARACTERISTICS
26 VCC = 12V CLOAD = 3nF
IN 1
24 DRVL
FALL TIME (ns)
22
DRVH 2
20
DRVH
DRVL
18
3
03229-B-005
16 0 25 50 75 100 JUNCTION TEMPERATURE (C) 125
Figure 5. DRVH Rise and DRVL Fall Times
Figure 8. DRVH and DRVL Fall Times vs. Junction Temperature
60
IN
50
TA = 25C VCC = 12V DRVH
1 DRVH
RISE TIME (ns) 40 DRVL 30
2
20
DRVL
03229-B-006
10 1 2 3 LOAD CAPACITANCE (nF) 4 5
Figure 6. DRVH Fall and DRVL Rise Times
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
40
VCC = 12V CLOAD = 3nF
DRVH
35 TA = 25 C VCC = 12V 30
35
DRVL
FALL TIME (ns)
RISE TIME (ns)
25
30
DRVL
20
DRVH
25
15
03229-B-007
20 0 25 50 75 100 JUNCTION TEMPERATURE ( C) 125
10 1 2 3 LOAD CAPACITANCE (nF) 4 5
Figure 7. DRVH and DRVL Rise Times vs. Junction Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 6 | Page 7 of 13 | www.onsemi.com
03229-B-010
03229-B-009
3
03229-B-008
ADP3418
60 TA = 25C VCC = 12V CLOAD = 3nF DRVL OUTPUT VOLTAGE (V)
5 TA = 25C CLOAD = 3nF 4
SUPPLY CURRENT (mA)
40
3
2
20
1
03229-B-011
0 0 200 400 600 800 FREQUENCY (kHz) 1000 1200
0 0 1 2 3 VCC VOLTAGE (V) 4 5
Figure 11. Supply Current vs. Frequency
Figure 13. DRVL Output Voltage vs. Supply Voltage
16 VCC = 12V CLOAD = 3nF fIN = 250kHz 15
SUPPLY CURRENT (mA)
14
13
12 0 25 50 75 100 JUNCTION TEMPERATURE (C) 125
Figure 12. Supply Current vs. Junction Temperature
Rev. 6 | Page 8 of 13 | www.onsemi.com
03229-B-012
03229-B-013
ADP3418 THEORY OF OPERATION
The ADP3418 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A more detailed description of the ADP3418 and its features follows. Refer to Figure 1.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn off to the Q2 turn on, and by internally setting the delay from the Q2 turn off to the Q1 turn on. To prevent the overlap of the gate drives during the Q1 turn off and the Q2 turn on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit ensures that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins to turn on. If the SW pin had not gone high first, the Q2 turn on is delayed by a fixed 120 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 240 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and is flowing through the high-side MOSFET body diode. To prevent the overlap of the gate drives during the Q2 turn off and the Q1 turn on, the overlap circuit provides an internal delay that is set to 40 ns. When the PWM input signal goes high, Q2 begins to turn off (after a propagation delay), but before Q1 can turn on, the overlap protection circuit waits for the voltage at DRVL to drop to approximately one sixth of VCC. Once the voltage at DRVL has reached this point, the overlap protection circuit waits for the 40 ns internal delay time. Once the delay period has expired, Q1 turns on.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the ADP3418 is disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST1. CBST2 and RBST are included to reduce the highside gate drive voltage and limit the switch node slew rate (referred to as a Boot-SnapTM circuit, see the Application Information section for more details). When the ADP3418 starts up, the SW pin is at ground; therefore, the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN, forcing the BST pin to VIN + VC (BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin pulls to ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver's output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
Rev. 6 | Page 9 of 13 | www.onsemi.com
ADP3418 APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3418, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn, such as a 4.7 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3418. maximum supply voltage. The average forward current is estimated by
I F ( AVG ) = Q GATE x f MAX
(3)
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET is chosen. The bootstrap capacitor must have a voltage rating that is able to handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined by:
C BST1 + C BST2 = 10 x QGATE VGATE
where fMAX is the maximum switching frequency of the controller. The peak surge current rating is calculated by V - VD I F ( PEAK ) = CC (4) R BST
MOSFET SELECTION
When interfacing the ADP3418 to external MOSFETs, there are a few considerations that the designer should be aware of. These help make a more robust design that minimizes stresses on both the driver and MOSFETs. These stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node.
(1) (2)
C BST1 VGATE = C BST1 + C BST2 VCC - VD
where:
HIGH-SIDE (CONTROL) MOSFETS
The high-side MOSFET is usually high speed to minimize switching losses (see any ADI Flex-ModeTM1 controller data sheet for more details on MOSFET losses). This usually implies a low gate resistance and a low input capacitance/charge device. Yet, there is also a significant source lead inductance that can exist. This depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3418 DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the gate's internal capacitance, which determines the speed at which the MOSFETs turn on and off. However, due to potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage across it when the high-side MOSFETs switch off. This creates a significant drain-source voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition can be referenced in literature from the MOSFET suppliers.
1
QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the 5 V to 10 V range, 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
C BST 1 = 10 x
QGATE VCC - VD
CBST2 can then be found by rearranging Equation 1 as
C BST2 = 10 x
QGATE - C BST1 VGATE
For example, an NTD60N02 has a total gate charge of approximately 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, one finds CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used for slew rate limiting to minimize the ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 to 2.2 is a good choice. The resistor needs to be able to handle at least 250 mW due to the peak currents that flow through it. A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the
Flex-Mode is protected by U.S. Patent 6,683,441.
Rev. 6 | Page 10 of 13 | www.onsemi.com
ADP3418
The MOSFET vendor should provide a maximum voltage slew rate at the drain current rating such that this can be designed around. Once this specification is had, the next step is to determine the maximum current expected to be seen in the MOSFET. This can be done by However, during the low-side turn off to high-side turn on, the SW pin does not contain information for determining the proper switching time; therefore, the state of the DRVL pin is monitored to go below one sixth of VCC and then a delay is added. However, due to the Miller capacitance and internal delays of the low-side MOSFET gate, one must ensure that the Miller to input capacitance ratio is low enough, and that the low-side MOSFET internal delays are not large enough, to allow accidental turn on of the low-side when the high-side turns on. A spreadsheet is available from ADI to assist designers with the proper selection of low-side MOSFETs.
I MAX = I DC ( per phase) + (VCC - VOUT )x
where:
D MAX f MAX x LOUT
(5)
DMAX is determined for the VR controller being used with the driver. Note that this current is divided roughly equally between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin). LOUT is the output inductor value. When producing the design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it also increases the switching losses in the high-side MOSFETs. The ADP3418 has been optimally designed with internal drive impedance that works with most MOSFETs to switch them efficiently while minimizing dV/dt. However, some high speed MOSFETs can require this external gate resistor, depending on the currents being switched in the MOSFET.
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed circuit boards: * * * * Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. Connect the PGND pin of the ADP3418 as close as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to the VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3418's DRVL does not exceed the thermal rating of the driver (see any ADI Flex-Mode controller data sheet for details). The next concern for the low-side MOSFETs is based on preventing them from inadvertently being switched on when the high-side MOSFET turns on. This occurs due to the draingate (Miller, also specified as Crss) capacitance of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a rate dV/dt), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal to VCC x (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the nonoverlap circuitry of the ADP3418, which attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap.
The circuit in Figure 15 shows how four drivers can be combined with the ADP3188 to form a total power conversion solution for generating VCC (CORE) for an Intel CPU that is VR 10.x-compliant. Figure 14 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the ADP3188 data sheet.
CBST1
CBST2
D1
RBST
CVCC
Figure 14. External Component Placement Example for the ADP3418 Driver
Rev. 6 | Page 11 of 13 | www.onsemi.com
03229-B-014
ADP3418
LI 370nH 18A R3 2.2 C7 4.7F C6 6.8nF Q1 NTD60N02 560F/4V x 8 L4 320nH/1.4m SANYO SEPC SERIES 5m EACH + C24 Q3 NTD110N02 Q4 NTD110N02 C31 + C8 12nF
VIN 12V
2700MF/16V/3.3A x 2 SANYO MV-WX SERIES
+ C1 D2 1N4148
1 BST 2 IN 3 OD 4 VCC
+ C2
VIN RTN DRVH 8 SW 7 PGND 6 DRVL 5
U2 ADP3418
VCC (CORE) 0.8375 V - 1.6V 95A TDC, 119A PK VCC (CORE) RTN
C5 4.7F R4 2.2 C12 12nF
D1 1N4148
1 BST 2 IN 3 OD 4 VCC
D3 1N4148 DRVH 8 SW 7 PGND 6 DRVL 5 Q8 NTD110N02 Q5 NTD60N02
U3 ADP3418
C10 6.8nF
C11 4.7F
10F x 18 MLCC IN SOCKET
L3 320nH/1.4m
C9 4.7F R5 2.2 C16 12nF Q7 NTD110N02
C3 + 100F
C4 1F
R2 137k 1%
1 VID4 2 VID3 3 VID2 4 VID1 5 VID0 3 OD 4 VCC 6 VID5 7 FBRTN 8 FB 9 COMP 10 PWRGD 11 EN 12 DELAY 13 RT 14 RAMPADJ ILIMIT 15
U1 ADP3188
VCC 28 PWM1 27 PWM2 26 PWM3 25
2 IN 1 BST
D4 1N4148 DRVH 8 SW 7 PGND 6 DRVL 5
U4 ADP3418
C14 6.8nF
C15 4.7F Q9 NTD60N02
FROM CPU PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 C22 1nF CCS1 560pF CCS2 1.5nF RCS1 RCS2 35.7k 84.5k RPH4 158k, 1% R6 2.2 C13 4.7F
Figure 15. VR 10.x-Compliant Intel CPU Supply Circuit
C20 12nF Q11 NTD110N02 Q12 NTD110N02 RPH2 RPH3 158k, RPH1 1% 158k, 158k, 1% 1%
Rev. 6 | Page 12 of 13 | www.onsemi.com
D5 1N4148
L4 320nH/1.4m
C21 1nF
CB 470pF
POWER GOOD
CA RA RB 1.21k 470pF 12.1k
CFB 22pF
ENABLE
CLDY 39nF
RLDY 470k
U5 ADP3418
1 BST 2 IN 3 OD 4 VCC
C16 6.8nF
DRVH 8 SW 7 PGND 6 DRVL 5
C19 4.7F Q13 NTD60N02
RT 137k 1%
L5 320nH/1.4m RTH1 100k, 5% NTC
C23 1nF
RLIM 150k 1%
C17 4.7F Q15 NTD110N02
Q16 NTD110N02
03229-B-015
ADP3418 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) 0.31 (0.0122)
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADP3418KRZ1 ADP3418KRZ-REEL1
1
Temperature Range 0C to 85C 0C to 85C
Package Description 8-Lead SOIC_N 8-Lead SOIC_N
Package Option R-8 R-8
Z = Pb-free part.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Rev. 6 | Page 13 of 13 | www.onsemi.com

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